The present disclosure relates to semiconductors and, more particularly, to methods for forming a vertical field effect transistor (VFET) and controlling the channel length.
Field effect transistors (FETs) are typically formed on semiconductor substrates and include a channel region disposed between source and drain regions, and a gate configured to electrically connect the source and drain regions through the channel region. Structures where the channel region is parallel to the main surface of the substrate are referred to as horizontal FET structures, while structures where the channel region is perpendicular to the main surface of the substrate are referred to as vertical FETS (VFETs). Thus, in a VFET device the direction of the current flow between the source and drain regions is normal to the main surface of the substrate.
A typical VFET device includes a vertical fin that extends upward from the substrate. The fin forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, while the gate is disposed on one or more of the fin sidewalls.
In other words, when viewing a VFET device from above, the channel region of the device is positioned vertically below one of the source/drain regions while the other source/drain region is positioned vertically below the channel region, i.e., the channel region is positioned vertically between a lower source/drain region and an upper source/drain region. In the architecture for a VFET, the contacted gate pitch may be decoupled from the gate length.